In general, a signal transmitted by a device in a digital system basically has two states aside from a floating state. The first state is designed to transmit a phenomenon corresponding to a logic high level (also called “logic high”, “High”, “1”, “ON” or “H level”). The second state is designed to transmit a phenomenon corresponding to a logic low level (also called “logic low”, “Low”, “0”, “OFF” or “L level”).
A particular signal potential that determines which of a logic high signal and a logic low signal is being transmitted depends upon a semiconductor device that forms a circuit related to the transmission.
For example, the most common circuit configurations used to produce a digital signal include a CMOS logic IC and a transistor-transistor logic (TTL) IC. In the CMOS logic IC, the logic low signal generally falls in a range of from a potential applied to a low-voltage terminal to a potential that is about 0.6 V higher than that applied to the low-voltage terminal, whereas the logic high signal is generally set in a range of from Vcc to Vcc-0.6 V if a potential applied to a high-voltage terminal is Vcc. As it is a well-known technical matter that a relationship between a signal potential and a logic level is determined depending on a device, this technical matter will not be specifically described below.
All sorts of data processing systems functioning as digital systems are usually provided with a plurality of external input terminals (a connector) for signal input. A plurality of input terminals (pins) for signal input are provided to a semiconductor integrated circuit such as a CPU which is installed in a data processing system. Sometimes a control terminal for switching operation modes of a CPU or the like is further provided to the semiconductor integrated circuit. The external input terminal has a function as an interface that inputs a logic signal having an H or L level, which is given from an external device, to transmit the signal to an internal circuit, such as a CPU and a memory. The control terminal has a function to switch the control information to be given to the internal circuit between the H and L levels, for example, depending upon whether it is grounded or not.
This kind of the external input terminal or the control terminal for a logic circuit has a high input impedance. For this reason, the potential is liable to be varied due to outside noise in a floating state. In order to avoid the influence of the outside noise even when the potential of the external input terminal is in the floating state, in conventional art, an external input terminal 1 is generally connected to a power source voltage Vcc through a pull-up resistor Rpu or alternatively grounded through a pull-down resistor Rpd as illustrated in FIGS. 13A and 13B.
An input buffer 2 having the external input terminal 1 is formed of an inverter circuit made up of a p-channel MOS transistor (abbreviated to “PMOS”) 3 and an n-channel MOS transistor (abbreviated to “NMOS”) 4, for example, as illustrated in FIGS. 13A and 13B. However, when the external input terminal 1 is connected with the pull-up resistor Rpu or the pull-down resistor Rpd, a leakage current sometimes flows into the external input terminal 1 using the resistor Rpu or Rpd as a course of the current.
For instance, as illustrated in FIG. 14, the leakage current can be reduced by providing a latch circuit 8, which is formed of a NMOS transistor 6 and a PMOS transistor 7 which are gate-controlled by an NMOS transistor 5, to an input node of an input buffer made up of two-stage inverter circuits 2a and 2b (see Patent Document 1, for example). When a signal (potential) having the H or L level is given to the external input terminal 1, the latch circuit 8 carries out a latch operation according to an output level of the input buffer (two-stage inverter circuits 2a and 2b) that operates in response to this signal. By doing this, the latch circuit 8 forcibly fixes the external input terminal 1 at the H or L level. At the same time, if the external input terminal 1 is in the floating state (open state), the latch circuit 8 turns off the NMOS transistor 5 by using an external signal S, and brings the NMOS transistor 6 and the PMOS transistor 7 into a conductive state (hereinafter referred to as “on”) and a nonconductive state (hereinafter referred to as “off”), respectively, by using the pull-up resistor Rpu. In so doing, the latch circuit 8 maintains the external input terminal 1 at the H level.
As a similar technology, a bus-hold circuit is known, which is provided for the purpose of preventing abnormal phenomena including the leakage current and oscillation of a semiconductor device and a data error which occur when the external input terminal becomes open (see Patent Document 2 and Non-patent Document 1, for example). When the external input terminal comes into the floating state, the bus-hold circuit maintains the preceding logic level given to the external input terminal. A bus-hold circuit of this type is occasionally used as a substitute for a pull-up resistor or a pull-down resistor in order to prevent the bus from coming into an undefined state.
A bus-hold circuit of this type is installed with an overvoltage protection circuit for blocking the current that flows from an external input terminal when the external input terminal of the bus-hold circuit is provided with a signal at a potential higher than the operating voltage of the bus-hold circuit (see Patent Document 3, for example).
As a general-purpose logic IC in which the above bus-hold circuit is realized, the 74VCX series and the like are available in the market.
Patent Document 1: Unexamined Japanese Patent Publication No. 9-161486.
Patent Document 2: U.S. Pat. No. 5,432,462.
Patent Document 3: U.S. Pat. No. 6,150,845.
Non-patent Document 1: “AN-5006J Designing with Bus-hold”; Fairchild Semiconductor Corporation; Application note; First edited March 1999 (revised September 1999); page 1-3.